1. Field of the Invention
The present invention generally relates to a charge-coupled device (CCD) imager and, more particularly, is directed to a CCD imager for use with a video telephone, for use in a rear portion of an automobile or the like and which provides a positive image picture and a mirror image picture.
2. Description of the Prior Art
A CCD pickup device or CCD imager utilizing a horizontal of two-phase drive CCD configuration is proposed as shown in FIG. 1.
Referring to FIG. 1, there is provided a CCD imager sensor portion 1 is of a type in the prior art. An image signal from the CCD image sensor portion 1 is supplied to a horizontal register portion 2, and an image signal from the horizontal register 2 is outputted through an output circuit 3 of a floating diffusion amplifier configuration.
The horizontal register 2 is constructed as a two-phase drive CCD. More specifically, in FIG. 1, reference numerals 4s, 4t, 5s and 5t respectively designate a first storage electrode, a first transfer electrode, a second storage electrode and a second transfer electrode which are respectively formed on a first storage portion, a first transfer portion, a second storage portion and a second transfer portion of transfer channels formed on a semiconductor substrate for forming a CCD, though not shown. The first storage electrode 4s, the first transfer electrode 4t, the second electrode 5s and the second transfer electrode 5t of a number are repeatedly arranged in one direction, in that order.
The adjacent first storage electrode 4s and first transfer electrode 4t are interconnected together, and a junction therebetween is interconnected through a bus line 4a to a first drive pulse input terminal 4. Also, the adjacent second storage electrode 5s and second transfer electrode 5t are interconnected together, and a junction therebetween is interconnected through a bus line 5a to a second drive pulse input terminal 5. The first and second drive pulse input terminals 4 and 5 are supplied with first and second drive pulses .phi.1 and .phi.2. The first and second drive pulses .phi.1 and .phi.2 are transfer clocks and are different in phase as shown in FIGS. 2A and 2B. In this case, they are so formed that when the first and second storage electrodes 4s and 5s and the first and second transfer electrodes 4t and 5t are supplied with the same voltage, the potential wells formed beneath the storage electrodes 4s and 5s become slightly deeper than those beneath the transfer electrodes 4t and 5t.
The horizontal register 2 is comprised of an effective bit portion 2a provided in response to the CCD image sensor portion 1 and having the number of bits corresponding to the number of its horizontal pixels and a dummy bit portion 2b of, for example, 16 bits continuous to the effective bit portion 2a. When the first and second drive pulses .phi.1 and .phi.2 are respectively supplied to the first and second drive pulse input terminals 4 and 5, a charge in the effective bit portion 2a is transferred through the dummy bit portion 2b to the output circuit 3 so that the output circuit 3 derives a normal image signal, i.e., a positive image signal.
Incidentally, in order to provide an image of video telephone, an image of the rear portion of an automobile or the like, a mirror image picture is convenient. Therefore, in the CCD imager shown in FIG. 1, a proposal shown in FIG. 3 is provided to generate a mirror image signal and a positive image signal which make a mirror image picture. In FIG. 3, like parts corresponding to those of FIG. 1 are marked with the same references and therefore need not be described in detail.
With reference to FIG. 3, the horizontal register 2 is provided in an opposing relation to the CCD image sensor portion 1 and is comprised of the effective bit portion 2a having bits of number corresponding to the number of horizontal pixels and dummy bit portions 2b and 2c of, for example, 16 bits continuous to the effective bit portion 2a at its both sides. The positive image output circuit 3 and a mirror image output circuit 6 are made continuous to the dummy bit portions 2b and 2c, respectively.
In each of the effective bit portion 2a and the dummy bit portions 2b and 2c of this horizontal register 2, similarly to the CCD imager shown in FIG. 1, the first storage electrode 4s, the first transfer electrode 4t, the second storage electrode 5s and the second transfer electrode 5t are repeatedly arranged in that order, whereas the potential wells beneath these electrodes 4s, 4t, 5s and 5t are constructed similarly to those of the example of FIG. 1.
In this example, the first storage electrodes 4s are coupled together by a bus line 4a.sub.1 to which a transfer clock is supplied, and a first drive pulse input terminal 4sp is led out from the bus line 4a.sub.1. The first transfer electrodes 4t are coupled together by a bus line 4a.sub.2 to which a transfer clock is supplied, and a second drive pulse input terminal 4tp is led out from the bus line 4a.sub.2. The second storage electrodes 5s are coupled together by a bus line 5a.sub.1 to which a transfer clock is supplied, and a third drive pulse input terminal 5sp is led out from the bus line 5a.sub.1. Further, the second transfer electrodes 5t are coupled together by a bus line 5a.sub.2 to which a transfer clock is supplied, and a fourth drive pulse input terminal 5tp is led out from the bus line 5a.sub.2.
When the positive image output circuit 3 derives a positive image signal to provide a positive image, the first drive pulse .phi.1 is supplied to the first and second drive pulse input terminals 4sp and 4tp as a transfer clock and the second drive pulse .phi.2 is supplied to the third and fourth drive pulse input terminals 5sp and 5tp as a transfer clock.
When the mirror image output circuit 6 derives a mirror image signal to provide a mirror image, the first drive pulse .phi.1 is supplied to the second and third drive pulse input terminals 4tp and 5sp as a transfer clock, while the second drive pulse .phi.2 is supplied to the first and fourth drive pulse input terminals 4sp and 5tp as a transfer clock. The rest of the arrangement of FIG. 3 is constructed the same as that of FIG. 1.
In the example of FIG. 3 as mentioned above, the first and second drive pulses .phi.1 and .phi.2 are selectively supplied to the first, second, third and fourth drive pulse input terminals 4sp, 4tp, 5sp and 5tp as the transfer clocks, whereby the positive image output circuit 3 can derive the positive image signal or the mirror image output circuit 6 can derive the mirror image signal.
The CCD imager shown in FIG. 3, however, needs four bus lines 4a.sub.1, 4a.sub.2, 5a.sub.1 and 5a.sub.2 to supply the first and second drive pulses .phi.1 and .phi.2 to the horizontal register 2, which provides the larger circuit pattern. Particularly, near the output circuits 3 and 6 provided at the two ends of the horizontal register 2, the pattern arrangement becomes considerably difficult.
Further, depending upon the operation conditions of the output circuits, a undesirable charge is mixed into the horizontal register from the output circuit which is not operated, for example, from the mirror image output circuit 6 when the positive image signal is obtained or from the positive image output circuit 3 when the mirror image signal is obtained.